Semiconductor memory device having a circuit for reducing frequency of proceeding refresh in data retention mode

ABSTRACT

A semiconductor memory device of the type needing refresh includes a circuit for reducing the frequency of refresh cycles in data retention mode. A circuit is provided for preventing deterioration to sensing margin of bit lines that may be decreased by a reduction of the frequency of refresh cycles. The deterioration is prevented by increasing the boosting level of word lines.

BACKGROUND OF THE INVENTION

(1) Field of the Invention

The present invention relates to a semiconductor memory device having a circuit for reducing the frequency of refresh cycles in data retention mode. It relates more particularly to a semiconductor memory device having reduced power consumption due to a reduction of the frequency of refresh cycles in data retention mode, but wherein decrease in boosting level of word lines that may occur by the reduction of frequency of the refresh cycle is prevented.

(2) Description of the Prior Art

Semiconductor memory devices are generally divided into a Read Only Memory (ROM) and Random Access Memory (RAM).

RAM includes Static RAM (SRAM) the memory cells of which are formed by flip-flops, each typically made up of four to six transistors; Dynamic RAM (DRAM) the memory cells of which are formed by transistor-capacitor combinations; and Pseudo-SRAM (PSRAM) which uses DRAM-type memory cells each with one MOS transistor and one capacitor, but the peripheral circuits of which have the same structure as the SRAM.

In random access memory, such as DRAM and PSRAM, where memory cells consist of one transistor and one capacitor, data stored in the memory cells decay with time. Accordingly, there is a need for a process of periodically refreshing (in what is commonly referred to as "refresh cycles") the memory cells in order to prevent the data from decaying.

A refresh process is similar to a conventional read/write operation. That is, a refresh cycle is carried out by reading out the data out of the memory and writing it back into the memory.

In prior art semiconductor devices such as DRAM and PSRAM which need refresh, the frequency of refresh cycles is the same in normal access mode and data retention mode (also known as self refresh mode). If the frequency of refresh cycles can be reduced in data retention mode, power consumption of the refresh circuit of the semiconductor memory device is reduced. In reducing the frequency of refresh cycles for achieving the above-identified advantage, the number of memory cells to be refreshed at one time may have to be increased as a function of reduction of the refresh frequency. As a result, the boosting level of word lines may decrease and result in deterioration in sensing margin of bit lines.

SUMMARY OF THE INVENTION

An object of the present invention is to solve the above-mentioned conventional disadvantage, and to provide a semiconductor memory device having a reduced frequency of refresh cycles in data retention mode and a corresponding reduction of power consumption, but wherein the sensing margin of bit lines is not deteriorated.

The above-mentioned object is achieved by a semiconductor memory device which comprises a memory refresh cycle controller for reducing the frequency of refresh cycles in data retention mode in response to a row address signal and a self-refresh signal, a word line boosting level generator for increasing the boosting level of word lines in data retention mode in response to the self refresh signal and a clock enable signal.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and further objects, features and advantages of the present invention will become more apparent from the following detailed description of taken in conjunction with the accompanying drawings, wherein:

FIG. 1 shows a schematic block diagram of a semiconductor device having a circuit for reducing the frequency of refresh cycles in data retention mode according to a preferred embodiment of the present invention;

FIG. 2 is a timing diagram showing a refresh cycle for a conventional memory device in data retention mode;

FIG. 3 is a schematic circuit diagram of the refresh cycle controller shown in FIG. 1 according to a preferred embodiment of the present invention; and

FIG. 4 is a schematic circuit diagram of the word line boosting level generator shown in FIG. 1 according to a preferred embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now to the drawings, a preferred embodiment of the present invention will be described.

FIG. 1 is a schematic block diagram of a semiconductor memory device having a circuit for reducing the frequency of refresh cycles in data retention mode according to a preferred embodiment of the present invention. The semiconductor memory device having the above-mentioned circuit comprises a memory 3 including a memory cell array, a row and column decoder and a sense amplifier. The memory 3 is connected to the refresh cycle controller 1 and a word line boosting level generator 2. The refresh cycle controller 1 operates to reduce the frequency of refresh cycles in data retention mode utilizing a row address signal from an address bus and a self-refresh signal φself. The φself signal is a signal generated internally to indicate that the memory device is in self refresh mode. The word line boosting level generator 2 operates to raise the boosting level of word lines utilizing a self-refresh signal φself and a clock-enable signal φce.

FIG. 2 shows a timing diagram of a refresh cycle for a conventional memory device during data retention mode. As shown, a conventional memory device typically enters data retention mode when a refresh signal RFSH changes to a low level after a chip-enable signal CE changes to a high level. After the memory refresh signal RFSH changes to a low level, the self-refresh signal φself changes to high level within a certain time (Ts).

FIG. 3 illustrates a schematic circuit diagram of the refresh cycle controller according to a preferred embodiment of the present invention. The refresh cycle controller 1 includes a first inverter I₁₁ having an input terminal connected to receive the self-refresh signal φself; a first NAND gate G₁₁ having one input terminal connected to the most significant bit RA_(MSB) of the row address and another input terminal connected to the output of the first inverter I₁₁ ; a second NAND gate G₁₂ having an input terminal connected to the complement of the most significant bit line RA_(MSB) of the row address and another input terminal connected to the output of the first inverter I₁₁ ; a second inverter I₁₂ having an input connected to the output terminal of the first NAND gate G₁₁ ; and a third inverter I₁₃ having an input connected to the output of the second NAND gate G₁₂.

The refresh cycle controller 1 operates as follows.

When the self-refresh signal φself is low, output of the first inverter I₁₁ becomes high. The most significant bit RA_(MSB) of the row address is gated through G and passes through and the complement of the most significant bit RA_(MSB) of the row address is gated by G and passes through I₁₃.

In data retention mode, the self-refresh signal φself is high and the output of the first inverter I₁₁ becomes low, thereby disabling gates G₁₁ and G₁₂. The output signals of the first and second NAND gates G₁₃ and G₁₂ are high, and outputs from I11 and I13 of the refresh cycle controller 1 become low, regardless of the input thereto. As a result, word lines that are decoded from the most significant bit RA_(MSB) are deactivated. Therefore, the frequency of refresh cycles for the memory cells of memory 3 becomes 2.sup.(the number of bit lines of row address line)-1. In other words, by invalidating the most significant bit line of row address lines, the frequency of refreshing the memory cells in data retention mode is reduced by half.

Although the most significant bit line of the row address lines is taken as an example in this preferred embodiment of the present invention, the present invention is not so limited. The frequency of refresh cycles can be further reduced by including other row address bits. For example, when two row address bits, such as the most significant bit and the second most significant bit, are used, the frequency of refresh cycles is further reduced to one-quarter. And when three significant bits are used, the frequency of refresh cycles is further reduced to one-eighth. The number of row address bits used can be further increased in similar manner.

When the frequency of refresh cycles in data retention mode is reduced as described above by the refresh cycle controller 1, the number of memory cells to be refreshed each time is increased by a function of the reduction of frequency of refresh cycles. Therefore, the boosting level of word lines may drop. However, the dropping of boosting level can be compensted by increasing the boosting level of word lines using the word line boosting level generator 2.

The structure and operation of the word line boosting level generator 2 will be described hereinafter.

FIG. 4 illustrates a schematic circuit diagram of the word line boosting level generator 2 according to the preferred embodiment of the present invention. The word line boosting level generator 2 includes a fourth inverter I₂₁ having an input terminal connected to receive the self-refresh signal φself; a fifth inverter I₂₂ having an input terminal connected to receive a clock-enable signal line φce; a sixth inverter I₂₃ having an input terminal connected to an output terminal of the fifth inverter I₂₂ ; a transmission gate G₂₁ having one control terminal connected between the self-refresh signal φself, another control terminal connected to receive the complement of φself from the output of the fourth inverter I₂₁, and an input terminal connected to the output of the sixth inverter I₂₃ ; a first field effect transistor (FET) TR₂₁ having a gate terminal connected to the output of the fourth inverter I₂₁, a drain terminal connected to the voltage supply V_(CC) and a gate terminal and a source terminal connected to the output of the transmission gate G₂₁ ; a first metal oxide semiconductor (MOS) capacitor C₂₁ having one terminal connected to the output of the transmission gate G₂₁ : a second metal oxide semiconductor capacitor C₂₂ connected between the output of the sixth inverter I₂₃ and one terminal of the first MOS capacitor C₂₁ ; a third field effect transistor TR₂₃ having a drain terminal connected to the voltage supply V_(CC), a gate terminal connected to a precharge signal line φpre, and a source terminal connected to a node of the first and second MOS capacitors C₂₁ and C₂₂ ; and a fourth field effect transistor TR₂₄ having a drain terminal connected to the node of the first and second MOS capacitors C₂₁ and C₂₂, a source terminal connected to a voltage supply V_(SS), and a gate terminal connected to an output disable signal φdis. The node of the first MOS capacitor C₂₁ and second MOS capacitor C₂₂ forms an output terminal φ_(WLE). The above transmission gate G₂₁ is an NMOS and a PMOS field effect transistor connected to each other. Its two gate terminals are the gate terminals of the two FETs and are used for controlling transmission of data from an input at the drain terminal of the transmission gate to the output at the source terminal of the transmission gate.

The operation of the word line boosting level generator 2 having the above-mentioned structure is as follows.

The third field effect transistor TR₂₃ precharges the output signal φ_(WLE) from voltage supply Vcc under control of precharge signal φpre. The output disable signal φ_(dis) allows a word line to drop to a low level when the device attains a precharged state after having been in an active state. When the output disable signal φdis is applied to the gate terminal of the fourth field effect transistor TR₂₄, the fourth field effect transistor TR₂₄ is turned on and the output signal φ_(WLE) is dropped to a low level. As a result, the output signal φ_(WLE) is disabled by the output disable signal φ_(dis). Thus, φ_(dis) must be dropped to a low level before φce rises from a low level to a high level. If φ_(dis) is kept at a high level, the level of φ_(WLE) cannot be boosted to a satisfactory level.

If a low level self-refresh signal φself is applied to the input terminal of the fourth inverter I₂₁ (as when the semiconductor memory device is not in data retention mode) so that the output of the fourth inverter I₂₁ is high, input to the PMOS gate terminal of the transmission gate G₂₁ is high and input to its NMOS gate terminal is low. As a result, the transmission gate G₂₁ shuts off.

When the transmission gate G₂₁ shuts off, the clock enable signal φce that passes through the fifth and sixth inverters I₂₂ and I₂₃ cannot pass through the transmission gate G₂₁. However, it is input to the second metal oxide semiconductor capacitor C₂₂. In this case, the boosting level of the word lines, which equals to the level of the output signal φ_(WLE), is a function of the electronic charge stored in the second metal oxide semiconductor capacitor C₂₂. If the level of the output signal φ_(WLE) rises, the potential of n-node rises, too. When the potential of node n rises to a certain level, the second field effect transistor TR₂₂ turns on. Thus, TR prevents node n from entering in a floating state when φself is low and TR₂₂ prevents node n from being raised by C₂₁ when φ_(WLE) is boosted by φ_(LE) in the case where φself is low. If node n attains a high level, a latch-up may occur in PMOS of the transmission gate G₂₁. As a result, the potential of node n is kept at a predetermined level.

If a high level self-refresh signal φself is applied to the input terminal of the fourth inverter I₂₁ (as when the semiconductor memory device is indata retention mode), the output signal of the fourth inverter I₂₁ becomes low. Input to the NMOS gate terminal of the transmission gate G₂₁ is therefore high while input to its PMOS gate is low. As a result, the transmission gate G₂₁ turns on.

When the transmission gate G₂₁ turns on, the clock-enable signal φce that passes through the fifth and sixth inverters I₂₂ and I₂₃ passes through the transmission gate G₂₁ to the first metal oxide semiconductor C₂₁, as it also passes to the second metal oxide semiconductor C₂₂. The electrical charge that is stored in the first and second metal oxide semiconductor capacitors C₂₁ and C₂₂ will become the output signal φ_(WLE). The level of output signal φ_(WLE) is now a function of the total capacitance of both the first and second metal oxide semiconductor capacitors C₂₁ and C₂₂, which is increased by the first metal oxide semiconductor capacitor C₂₁. The increase in stored electric charge prevents a decrease of the boosting level word lines which may result from an increase of the number of word lines to be refreshed when the frequency of the refresh cycles is reduced in data retention mode.

As mentioned above, the present invention provides a semiconductor memory device having a circuit for reducing the frequency of refresh cycles in data retention mode, but the sensing margin of bit lines of which is not deteriorated because the boosting level of word lines is raised. 

What is claimed is:
 1. A semiconductor memory device comprising: a memory including a plurality of word lines for accessing data stored in the memory;a refresh cycle controller for controlling the frequency of the refresh cycles in data retention mode based upon at least one row address bit and a self-refresh signal, the refresh cycle controller comprising means for separately gating said at least one row address bit and a complement of said at least one row address bit and a complement of said at least one row address bit in response to said self-refresh signal; and a word line boosting level generator for increasing a boosting level of said word lines to said memory in data retention mode in response to said self-refresh signal and a clock-enable signal.
 2. A semiconductor memory device as in claim 1, wherein said gating means include:a first inverter having an input terminal receiving said self refresh signal; a first NAND logic circuit having input terminals respectively connected to said at least one row address bit and an output terminal of said first inverter; and a second NAND logic circuit having input terminals respectively connected to a complement of said at least one row address bit and the output terminal of said first inverter.
 3. A semiconductor memory device as in claim 1, wherein said gating means includes:a first inverter having an input terminal receiving said self-refresh signal; a first NAND gate having input terminals respectively connected to said at least one row address bit and an output terminal of said first inverter; a second NAND gate having input terminals respectively connected to a complement of said at least one row address bit and the output terminal of said first inverter; a second inverter having an input terminal connected to an output terminal of the first NAND gate; and a third inverter having an input terminal connected to an output terminal of the second NAND gate.
 4. A semiconductor memory device comprising:a memory including a plurality of word lines for accessing data stored in the memory; a refresh cycle controller for controlling the frequency of refresh cycles in data retention mode based on at least one row address bit and a self-refresh signal; and a word line boosting level generator for increasing a boosting level of said word lines to said memory in data retention mode in response to said self-refresh signal and a clock-enable signal, said word line boosting level generator comprising:a fourth inverter receiving said self-refresh signal; a fifth inverter receiving said clock-enable signal; a sixth inverter having an input terminal connected to an output terminal of said fifth inverter; a transmission gate having a control terminal connected between the self-refresh signal and an output terminal of the fourth inverter, and an input terminal connected to an output terminal of the sixth inverter; a first field effect transistor having a gate terminal connected to the output terminal of the fourth inverter, a drain terminal connected to a voltage supply Vcc, and a source terminal connected to an output terminal of the transmission gate; a second field effect transistor having a drain terminal connected to the voltage supply Vcc and a gate terminal and a source terminal connected to the output terminal of the transmission gate; a first metal oxide semiconductor capacitor having one terminal connected to the output terminal of the transmission gate; a second metal oxide semiconductor capacitor having one terminal connected to the output terminal of the sixth inverter, and another terminal connected to another terminal of the first MOS capacitor; a third field effect transistor having a drain terminal connected to the voltage supply Vcc, a gate terminal connected to a precharge signal line, and a source terminal connected to a node formed by said another terminals respectively of the first and second metal oxide semiconductor capacitors; and a fourth field effect transistor having a drain terminal connected to the node of the first and second metal oxide semiconductor capacitors, a source terminal connected to a voltage supply Vss, and a gate terminal connected to an output disable signal. 